QUALIFIER_SLICE_MODE=SLICE_A, EXT_CLK_ENABLE=INTERNAL_CLOCK_SIGNA, CONCAT_ORDER=SELF_LOOP, QUALIFIER_MODE=ENABLE, CONCAT_ENABLE=EXTERNAL_DATA_PIN, QUALIFIER_PIN_MODE=SGPIO8, CLK_SOURCE_PIN_MODE=SGPIO8, CLK_SOURCE_SLICE_MODE=SLICE_D
SGPIO multiplexer configuration registers.
| EXT_CLK_ENABLE | Select clock signal. 0 (INTERNAL_CLOCK_SIGNA): Internal clock signal (slice) 1 (EXTERNAL_CLOCK_SIGNA): External clock signal (pin) |
| CLK_SOURCE_PIN_MODE | Select source clock pin. 0 (SGPIO8): SGPIO8 1 (SGPIO9): SGPIO9 2 (SGPIO10): SGPIO10 3 (SGPIO11): SGPIO11 |
| CLK_SOURCE_SLICE_MODE | Select clock source slice. Note that slices D, H, O and P do not support this mode. 0 (SLICE_D): Slice D 1 (SLICE_H): Slice H 2 (SLICE_O): Slice O 3 (SLICE_P): Slice P |
| QUALIFIER_MODE | Select qualifier mode. 0 (ENABLE): Enable 1 (DISABLE): Disable 2 (SLICE_SEE_BITS_QUAL): Slice (see bits QUALIFIER_SLICE_MODE in this register) 3 (EXTERNAL_SGPIO_PIN): External SGPIO pin (SGPIO8, SGPIO9, SGPIO10, or SGPIO11) |
| QUALIFIER_PIN_MODE | Select qualifier pin. 0 (SGPIO8): SGPIO8 1 (SGPIO9): SGPIO9 2 (SGPIO10): SGPIO10 3 (SGPIO11): SGPIO11 |
| QUALIFIER_SLICE_MODE | Select qualifier slice. 0 (SLICE_A): Slice A, but for slice A slice D is used. 1 (SLICE_H): Slice H, but for slice H slice O is used. 2 (SLICE_I): Slice I, but for slice I slice D is used. 3 (SLICE_P): Slice P, but for slice P slice O is used. |
| CONCAT_ENABLE | Enable concatenation. 0 (EXTERNAL_DATA_PIN): External data pin 1 (CONCATENATE_DATA): Concatenate data |
| CONCAT_ORDER | Select concatenation order 0 (SELF_LOOP): Self-loop 1 (2_SLICES): 2 slices 2 (4_SLICES): 4 slices 3 (8_SLICES): 8 slices |
| RESERVED | Reserved |